As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in a variety of electronic devices.
Generally, a solid state storage device comprises a non-volatile memory. After data are written to the non-volatile memory, if no electric power is supplied to the solid state storage device, the data are still retained in the non-volatile memory.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 comprises an interface controller 101 and a non-volatile memory 105. The non-volatile memory 105 further comprises a memory cell array 109 and an array control circuit 111.
The solid state storage device 10 is connected with a host 14 through an external bus 12. For example, the external bus 12 is a USB bus, a SATA bus, a PCIe bus, a M.2 bus, a U.2 bus, or the like.
Moreover, the interface controller 101 is connected with the non-volatile memory 105 through an internal bus 113. According to a write command from the host 14, the interface controller 101 controls the array control circuit 111 to store the write data from the host 14 to the memory cell array 109. Alternatively, according to a read command from the host 14, the interface controller 101 controls the array control circuit 111 to acquire a read data from the memory cell array 109. In addition, the read data is transmitted to the host 14 through the interface controller 101.
Generally, the interface controller 101 stores a default read voltage set. During a read cycle, the interface controller 101 transmits an operation command to the array control circuit 111 of the non-volatile memory 105 through the internal bus 113. Consequently, the interface controller 101 allows the array control circuit 111 to read the previously-stored data from the memory cell array 109 of the non-volatile memory 105 according to the default read voltage set.
The interface controller 101 further comprises an error correction code (ECC) circuit 104 for correcting the error bits of the read data. After the error bits of the read data are corrected, the accurate read data is transmitted to the host 14. However, if the ECC circuit 104 is unable to successfully correct all bits of the read data, the accurate read data cannot be outputted to the host 14. Under this circumstance, the interface controller 101 provides other read retry voltage sets. According to the read retry voltage sets, the interface controller 101 performs a read retry operation on the non-volatile memory 105. The operating principles will be described as follows.
Depending on the data amount to be stored in the memory cell, the memory cells may be classified into four types, i.e. a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC) and a quad-level cell (QLC). The SLC can store only one bit of data per cell. The MLC can store two bits of data per cell. The TLC can store three bits of data per cell. The QLC can store four bits of data per cell. The memory cell array 109 can be a SLC memory cell array, a MLC memory cell array, a TLC memory cell array or a QLC memory cell array.
In the memory cell array 109, each memory cell comprises a floating gate transistor. By adjusting the number of hot carriers injected into a floating gate of the floating gate transistor, the array control circuit 111 controls the storing state of the floating gate transistor. In other words, the floating gate transistor of each SLC has two storing states, the floating gate transistor of each MLC has four storing states, the floating gate transistor of each TLC has eight storing states, and the floating gate transistor of each QLC has sixteen storing states.
FIG. 2A schematically illustrates the ideal threshold voltage distribution curves of single-level cells in different storing states. According to the number of injected hot carriers, the single-level cell has two storing states “Erase” and “A”. Before the hot carriers are injected into the memory cell, the memory cell is in the storing state “Erase”. After the hot carriers are injected into the memory cell, the memory cell is in the storing state “A”. The memory cell in the storing state “A” has the higher threshold voltage, and the memory cell in the storing state “Erase” has the lower threshold voltage. After an erase cycle is performed on the memory cell, the memory cell is restored to the storing state “Erase”, and no hot carriers are retained in the memory cell.
In practice, even if many memory cells are in the same storing state during the program cycle, the threshold voltages of these memory cells are not all identical. That is, the threshold voltages of these memory cells are distributed in a specified distribution curve with a median threshold voltage. As shown in FIG. 2A, the median threshold voltage of the memory cells in the storing state “Erase” is Ver, and the median threshold voltage of the memory cells in the storing state “A” is Va. For example, the median threshold voltage for a greater number of memory cells in the storing state “A” is Va.
Please refer to FIG. 2A again. According to the above characteristics of the single-level cell, a default read voltage set including one read voltage Vra is defined. During the read cycle, the interface controller 101 provides the read voltage Vra of the default read voltage set to the array control circuit 111 in order to detect the storing states of the single-level cells of the memory cell array 109.
As shown in FIG. 2A, the storing states of the single-level cells are determined according to the read voltage Vra of the default read voltage set. For example, the read voltage Vra is provided from the array control circuit 111 to the memory cell array 109. If the threshold voltage of the memory cell is higher than the read voltage Vra and the memory cell cannot be turned on, the array control circuit 111 judges that the memory cell is in the storing state “A”. Whereas, if the threshold voltage of the memory cell is lower than the read voltage Vra and the memory cell is turned on, the array control circuit 111 judges that the memory cell is in the storing state “Erase”.
Similarly, the default read voltage set for the multi-level cell includes three read voltages. The four storing states of the multi-level cells are determined according to three read voltages of the default read voltage set.
Similarly, the default read voltage set for the triple-level cell includes seven read voltages. The eight storing states of the triple-level cells are determined according to seven read voltages of the default read voltage set.
Similarly, the default read voltage set for the quad-level cell includes fifteen read voltages. The sixteen storing states of the quad-level cells are determined according to fifteen read voltages of the default read voltage set.
However, since the operating conditions of the solid state storage device 10 are different, the threshold voltage distribution curves of the memory cells in the memory cell array 109 are possibly distorted or shifted. If the threshold voltage distribution curves of the memory cells are seriously distorted or shifted, the memory cells are in a failure mode. In the failure mode, the interface controller 101 cannot generate the accurate read data. Some types of the failure mode of the single-level cells will be described as follows.
FIG. 2B schematically illustrates the shift of the threshold voltage distribution curves of single-level cells in a read disturb failure mode. After the single-level cells have been read many times, the threshold voltages of a portion of the memory cells with the storing state “Erase” will be increased. If the threshold voltage of the memory cell is increased to a very high value, the portion of the memory cell is misjudged to have the storing state “A”. Under this circumstance, the data is erroneously read. Meanwhile, the memory cell is in the read disturb failure mode.
FIG. 2C schematically illustrates the shift of the threshold voltage distribution curves of single-level cells in a room temperature data retention (RTDR) failure mode. When the single-level cells are operated in the room temperature situation, the hot carriers in the floating gates are possibly lost. Consequently, the threshold voltages of a portion of the memory cells with the storing state “A” are decreased. If the threshold voltage of the memory cell is decreased to a very low value, the portion of the memory cell is misjudged to have the storing state “Erase”. Under this circumstance, the data is erroneously read. Meanwhile, the memory cell is in the room temperature data retention (RTDR) failure mode.
FIG. 2D schematically illustrates the shift of the threshold voltage distribution curves of single-level cells in a high temperature data retention (HTDR) failure mode. When the single-level cells are operated in the high temperature situation, the hot carriers in the floating gates are easily lost and the threshold voltage distribution curve of the storing state “A” are shifted to the left. That is, the threshold voltages of all memory cells with the storing state “A” are decreased. If the threshold voltage of the memory cell is decreased to a very low value, the memory cell is misjudged to have the storing state “Erase”. Under this circumstance, the data is erroneously read. In other words, the memory cell is in the high temperature data retention (HTDR) failure mode. In the HTDR failure mode, the interface controller 101 judges the storing states of the single-level cells according to a read voltage Vra′.
FIG. 2E schematically illustrates the shift of the threshold voltage distribution curves of single-level cells in an F-poly coupling failure mode. When the single-level cells are programmed, the threshold voltages of the neighboring memory cells are influenced and the threshold voltage distribution curve of the storing state “A” are shifted to the right and widened. Under this circumstance, the data is erroneously read. Meanwhile, the memory cell is in the F-poly coupling failure mode.
FIG. 2F schematically illustrates the shift of the threshold voltage distribution curves of single-level cells in an endurance failure mode. When the single-level cells have been programmed and erased many times, the threshold voltage distribution curve of the storing state “A” are shifted to the right and widened. Under this circumstance, the data is erroneously read. Meanwhile, the memory cell is in the endurance failure mode.
As mentioned above, if the threshold voltage distribution curves of memory cells in the memory cell array 109 are seriously distorted or shifted, the interface controller 101 cannot generate the accurate read data. That is, when the interface controller 101 determines the storing states of the single-level cells according to the read voltage Vra, the read data contains so many error bits. Since the ECC circuit 104 is unable to successfully correct all bits of the read data, the data is erroneously read. Meanwhile, the interface controller 101 has to provide another read retry voltage Vra′ to perform the read retry process.
FIG. 3 is a flowchart illustrating an error correction method for a solid state storage device according to the prior art. During the read cycle, the interface controller 101 firstly performs a decoding process S1. In the decoding process S1, a hard decoding operation is performed according to a default read voltage set. That is, the interface controller 101 provides the default read voltage set to the non-volatile memory 105, and the ECC circuit 104 performs the hard decoding operation to correct the read data.
If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process S1 is passed. Consequently, the accurate read data is transmitted from the interface controller 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, the read data is not accurately acquired and the decoding process S1 is failed. Then, the interface controller 101 performs a read retry process.
After the interface controller 101 enters the read retry process, a decoding process S2 is firstly performed. In the decoding process S2, a hard decoding operation is performed according to a read retry voltage set. For example, the interface controller 101 provides the read retry voltage set to the non-volatile memory 105 to acquire the read data. Then, the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process S2 is passed. Consequently, the accurate read data is transmitted from the interface controller 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, the read data is not accurately acquired and the decoding process S2 is failed.
Generally, plural read retry voltage sets (e.g., M read retry voltage sets) are stored in the interface controller 101. If the decoding operation is successfully done according to one of the plural read retry voltage sets, it means that the decoding process S2 is passed. Whereas, if the data cannot be successfully decoded according to all of the plural read retry voltage sets, it means that the decoding process S2 is failed. Then, the interface controller 101 performs a decoding process S3. Obviously, the time period of performing the decoding process S2 is longer than the time period of performing the decoding process S1.
In the decoding process S3, a soft decoding operation is performed according to the read retry voltage set. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, while the soft decoding operation is performed, the interface controller 101 acquires a read data according to many read retry voltage sets. In other words, the time period of performing the soft decoding operation is longer. That is, the time period of performing the decoding process S3 is longer than the time period of performing the decoding process S2.
Similarly, if the decoding operation is successfully done by the interface controller 101, it means that the decoding process S3 is passed. Consequently, the accurate read data is transmitted from the interface controller 101 to the host 14. Whereas, if the data cannot be successfully decoded by the interface controller 101, it means that the decoding process S3 is failed. Under this circumstance, the interface controller 101 confirms that the accurate read data cannot be acquired and generates a failed message to the host 14 to indicate that the whole decoding process is failed.
As mentioned above, if the decoding process S1 is failed, the interface controller 101 enters the read retry process. In the read retry process, the interface controller 101 has to perform the decoding process S2 at first. If the interface controller 101 confirms that the decoding process S2 is failed, the interface controller 101 performs the decoding process S3. If the interface controller 101 confirms that the decoding process S3 is failed, the interface controller 101 issues the failed message to the host 14.
With increasing development of the semiconductor manufacturing process, the memory cell array with a 3D structure has been introduced into the market. Similarly, in many operating conditions, the memory cell array with the 3D structure is possibly suffered from many failure modes and subjected to many read retry processes. Therefore, it is important to reduce the time period of performing the read retry process.